Conventional methods of manufacturing integrated circuit devices include a fabrication (FAB) process, i.e., forming cells on a substrate that make up the integrated circuit device, and an assembly process, i.e., packaging the cells on the substrate into chips. Furthermore, an electrical die sorting (EDS) process may be performed between the fabrication process and the assembly process to test electrical properties of the cells formed on the substrate.
In particular, the EDS process may be performed to determine if the cells formed on the substrate are defective. Once the EDS process is completed, the defective cells may be removed before the assembly process is initiated. Thus, implementing the EDS process may reduce the time and effort involved in carrying out the assembly process. In addition, the defective cells may be located in advance and may be repaired and/or regenerated.
A conventional EDS process may include a pre-laser test and a post-laser test. The pre-laser test may be used to identify the defective cells. The post-laser test may be used to repair the identified defective cells and re-test the repaired cells to determine if the repairing process was successful. The process of repairing the cells may include cutting a wiring connected to a defective cell by irradiating a laser beam onto the wiring and replacing the defective cell with a redundancy cell built into the chip. The wiring to be cut by the exposure to the laser beam is typically called a fuse pattern. An insulation layer, i.e. a window layer, for protecting the fuse pattern and defining a fuse portion is typically provided on the fuse pattern.
Examples of conventional fuse patterns are disclosed in U.S. Pat. No. 6,100,117 to Hao et al. and U.S. Pat. No. 6,180,503 to Tzeng et al. As discussed in these patents, a portion of a bit line of an integrated circuit device, for example, an integrated circuit memory device, may be used as the fuse pattern. In other words, the bit line may be extended into a fuse portion of the device and this portion of the bit line may be used as the fuse pattern.
When a portion of the bit line is used as the fuse pattern it may be difficult to form an opening exposing the fuse pattern in the fuse region because the bit line is typically covered by multiple insulation layers, metal wirings and the like. Accordingly, the opening exposing the fuse pattern may be deep and may require additional processing time due to the extra depth. Thus, the overall productivity of the process may be reduced. Furthermore, it may also be difficult to control a thickness of the window layer when the window layer is disposed in a deep opening.
Alternatively, upper electrodes of capacitors or a metal wiring may be used as the fuse pattern instead of the bit line. An example of using the upper electrode of the capacitor as the fuse pattern is discussed in Korean Patent Laid-Open Publication No. 2001-61081 and an example of using a metal wiring as the fuse pattern is discussed in Japanese Patent Laid-Open Publication No. Hei 11-87646 corresponding to U.S. Pat. No. 6,040,614 to Kitaguchi et al.
When the upper electrode of the capacitor or the metal wiring is used as the fuse pattern, an underlying structure of the fuse pattern may be damaged by a laser beam used to cut the fuse pattern. Accordingly, when the metal wiring is used as the fuse pattern, a buffer layer is typically formed under the fuse pattern to reduce any possible damage that may be caused by the laser beam.
An example of using a metal wiring as the fuse pattern combined with a buffer layer under the fuse pattern is discussed in Korean Patent Laid-Open Publication No. 2001-37795. As discussed therein, the buffer layer is a plug type buffer layer. The plug type buffer layer may be formed by forming a groove on a thin film and providing buffer layer material in the groove. In particular, an insulation layer may be formed on an underlying structure such as a bit line, a portion of the insulation layer may be etched to form a groove and a material for forming a buffer layer may be provided in the groove. A planarizing process, for example, a chemical mechanical polishing (CMP) process, or an etch back process may be performed to remove a portion of the buffer material, thereby allowing the buffer material to remain substantially within the groove to form the buffer layer plug. The fuse pattern may be formed on the insulation layer in which the buffer layer plug is provided.
Thus, according to the teachings of these references, damage caused to the substrate by the laser beam used to cut the fuse pattern may be reduced by the presence of the buffer layer. However, fabrication of the buffer layer plug may be complicated and time consuming. Accordingly, improved fuse structures and methods of manufacturing fuse structures may be desired.